1. Field of the Invention
This invention relates to a method for fabricating a semiconductor device, and more particularly to a method for forming self-aligned landing pads.
2. Description of Related Art
Currently, the line width of the semiconductor fabrication process is already at the sub-micron level. Downsizing the line width of the fabrication process is an approach to improve the efficiency of a semiconductor device, and reduce the fabrication cost as well. Downsizing a semiconductor device can be partially accomplished by improving the resolution of some fabrication processes, such as photolithography dry etching processes. More advanced exposure equipment and more sensitive photoresists are certainly required for a sub-micron photolithography process. More precise and advanced etching equipment and methods are also needed for transferring patterns more correctly and successfully. Although developing advanced equipment and methods helps to downsize a semiconductor device, the task is still mainly dependent on minimizing the structure of a semiconductor device.
For example, in order to minimize a semiconductor device, a conducting structure used to connect a bit line or a node in an upper layer of the source/drain regions of a transistor in a lower layer has to be minimized. Methods according to the foregoing goal have been developed and used, wherein the methods include placing a narrow polysilicon plug between the bit line and the source/drain regions underneath. However, forming a narrow polysilicon plug on the source/drain regions and then forming a bit line over the polysilicon plug require very precise photolithography processes that are difficult to accomplish when line width is at the sub-micron level.
FIGS. 1A through 1C are cross-sectional views showing a conventional landing pad. Referring to FIG. 1A, a provided substrate 100 contains transistor 106 consisting of a gate 102 and a spacer 104, wherein the gate 102 further includes a conducting layer (not shown) and a insulator (not shown). A conducting layer 110 is formed to cover the entire substrate 100.
FIG. 1B shows formation of a patterned photoresist layer 112 on the conducting layer 110. The pattern is then transferred onto the conducting layer 110.
In FIG. 1C, a portion of the conducting layer 110 is removed to expose the gate 102. The sections of divided conducting layer 110' work as the landing pads between transistors 106. Since the patterns for forming the landing pads are separated, the distance between landing pads is limited by the resolution of the photolithography. Generally, the distance between landing pads has to be greater than 0.22 .mu.m. As the design rule is downsized, the limitation of the photolithography resolution downsizes the windows of photolithography process, and that increases the difficulty of the fabrication process.